To keep with increasing demand for improvements in data processing capability, it is essential that today's semiconductor devices (chips) operate at higher and higher speeds. As a result, many circuit problems have arisen, including increased cross-talk noise between adjacent signal lines (traces), improper characteristic impedance matching, etc. Overcoming these problems is made all the more difficult by the accompanying demand for higher circuit densities within both the chip and the circuitized substrate (e.g., a printed circuit board or chip carrier substrate) having the chip mounted thereon and electrically coupled thereto. Adding still further to the difficulties of finding adequate solutions for such problems is the high demand for miniaturization in many of the end products (e.g., computers, servers, mainframes, etc.) which use such chips and accompanying substrates.
As defined herein, the present invention addresses the problem associated with impedance disruption when signals pass along highly dense signal lines in a compact, circuitized substrate electrically coupled to one or more semiconductor chips specifically designed for operating at higher speeds. Such disruption is deleterious to effective signal passage and, ultimately, effective operation of the end product. As further defined herein, the invention is able to do so while providing a highly dense plurality of conductive thru-holes within the substrate to further maximize the circuit design's operational characteristics. By the term “thru-hole” as used herein is meant to include what are also referred to in the art as “vias”; that is, conductive openings within the substrate body designed to interconnect designated conductive layers (especially signal planes) to pass signals there-between. A “via” may be in the form of an opening extending substantially from an outer surface of the substrate to a designated internal plane, in which case it is also referred to in the art as a “blind via”. These are distinguishable over vias which are positioned entirely within the substrate and thus encapsulated by the substrate's dielectric material, which vias are also referred to as, simply, internal or buried “vias.” It is also within the scope of the invention to utilize thru-holes which extend entirely through the substrate thickness, in which case these are referred to as plated through holes (or simply as PTHs). The term “thru-hole” as used herein is meant to include all three such openings.
Various substrates, primarily printed circuit boards (hereinafter also referred to as PCBs), have addressed impedance issues, including control.
In U.S. Pat. No. 6,775,122, issued Aug. 10, 2004, there is described a printed circuit board which includes two conductive planes. A “via” spans the planes, and an impedance “component” is placed in the via. The impedance component is coupled to both of the planes and allegedly provides an impedance level for the planes without the use of traces or hand soldering of components.
In U.S. Pat. No. 6,726,488, issued Apr. 27, 2004, there is described a high-frequency printed circuit board which allegedly enables matching of characteristic impedance at a connection of a line conductor and a through conductor and inhibition of unnecessary radiation of an electromagnetic wave from between the line conductor and a same plane ground conductor. This allegedly provides good high-frequency signal transmission characteristics, even in a high-frequency band such as a microwave band and a millimeter waveband.
In U.S. Pat. No. 6,707,685, issued Mar. 16, 2004, there is described a multi-layer printed circuit board which includes an insulating substrate having, on a central part of its top surface, a semiconductor device mounting portion and having, on its under surface, an external electrode. The insulating substrate includes multilayered wiring having a first group of parallel wiring lines, a second group of parallel wiring lines arranged orthogonal thereto, and a group of through conductors for providing electrical connection there-between. Power is supplied from the external electrode to the semiconductor device through built-in capacitors formed there-within. The built-in capacitors are connected in parallel that have different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component. At an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is equal to or below a predetermined value.
In U.S. Pat. No. 6,677,831, issued Jan. 13, 2004, there is described a method to control differential signal trace impedance by allowing flexible use of different signal trace width and spacing while maintaining constant differential impedance within a printed circuit board. Differential impedance of a signal pair is determined by the geometry of individual traces and the spacing between traces. The value of the differential impedance is inversely proportional to signal trace width and directly proportional to signal trace spacing. By decreasing or increasing trace width and spacing simultaneously, a constant differential impedance is allegedly achieved.
In U.S. Pat. No. 6,405,431, issued Jun. 18, 2002, there is described a method for manufacturing a built-up multi-layer printed circuit board in which a YAG laser is used to form a “via hole” in the board. The method includes the steps of forming a first printed circuit pattern on a copper clad laminate by applying a general photo-etching process (the laminate having a copper foil on the one face thereof), stacking a resin-coated (on one face) copper foil on the laminate with the first printed circuit pattern formed thereon, and heating and pressing this structure. Next, a YAG laser is used to form a “via hole” at a predetermined position by removing the resin-coated copper foil, then carrying out an electro-less and electro copper plating on the board with the “via hole” formed therein to form a plated layer. A second printed circuit pattern is then formed on the plated layer to electrically connect the layers on which the first and second printed circuit patterns are formed.
In U.S. Pat. No. 6,119,335, issued Sep. 19, 2000, there is described a method for manufacturing a built-up multi-layer printed circuit board for use in computers, video tape recorders, and portable telephones in which a resin-clad copper foil is stacked on a copper-clad laminate after forming a printed circuit layer, following which this structure is heated and pressed. Then, beams of an Nd-YAG laser are irradiated to remove the copper-clad layer, following which beams of a CO-2 laser are irradiated to remove the residual resin insulator, thereby forming a “via hole”. Circuit patterns are then formed on the board on which the “via hole” has been formed.
In U.S. Pat. No. 5,880,018, issued Mar. 9, 1999, there is described a method of making an interconnect structure having a dielectric layer with a low dielectric constant. In this method, portions of a silicon dioxide layer lying adjacent a conductive interconnect are removed to expose portions of a silicon nitride etch stop layer. A dielectric layer having a low dielectric constant is then formed overlying the conductive interconnect and the exposed portions of the silicon nitride etch stop layer. A portion of the dielectric layer is then removed to expose the top surface of the conductive interconnect to leave portions of the dielectric layer between adjacent conductive interconnects. The resulting interconnect structure allegedly has reduced cross-talk between conductive interconnects while avoiding disadvantages of reduced thermal dissipation and increased mechanical stress.
In U.S. Pat. No. 5,677,241, issued Oct. 14, 1997, there is described a method of forming integrated circuitry which includes providing a pair of spaced and adjacent electrically conductive elongated lines and providing electrically insulating material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. The electrically insulating material is provided by depositing electrically insulating material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at one end which is subsequently sealed. The formed circuitry includes a pair of spaced and adjacent electrically conductive elongated lines being encapsulated with an electrically insulating material. A top sealed elongated void is provided relative to the electrically insulating material between the lines, allegedly facilitating electrical isolation of the lines from one another.
It is thus seen from the above patents that various approaches have been attempted with respect to improving substrate construction and particularly with respect to enhanced signal passage. Some of these patents have also addressed impedance issues. The present invention provides another solution, this with respect to impedance control, and in an expeditious manner while not requiring significant cost increases or complex manufacturing processes. The solution provided herein results in a compact, miniaturized structure capable of meeting many of today's design and operational requirements. It is believed that such an invention would constitute a significant advancement in the art, as would various products (e.g., information handling systems) capable of using this new and unique substrate.